CM_TFR_ST_STS=Val_0x0, MASTER_IDLE=Val_0x0
Present State Register
| SCL_LINE_SIGNAL_LEVEL | This bit is used to check the SCL line level to recover from errors and for debugging. It reflects the value of synchronized SCL signal. This is valid in Master mode only. |
| SDA_LINE_SIGNAL_LEVEL | This bit is used to check the SDA line level to recover from errors and for debugging. It reflects the value of synchronized SDA signal. This is valid in Master mode only. |
| CURRENT_MASTER | This bit is used to check whether the master is current master or not. The current master is the master that owns the SCL line. If this bit is set to 0x0, the master is not current master and requires to request the ownership before initiating any transfer on the line. If this bit is set to 0x1, the master is the current master and can initate the transfers on the line. |
| CM_TFR_STS | Transfer Type Status This field indicates the type of transfer currently executing by the I3C. This is valid in Master mode only 0x0: IDLE (Controller is in IDLE state, waiting for commands) 0x1: Broadcast CCC write transfer 0x2: Directed CCC write transfer 0x3: Directed CCC read transfer 0x4: ENTDAA address assignment transfer 0x5: SETDASA address assignment transfer 0x6: Private I3C SDR write transfer 0x7: Private I3C SDR read transfer 0x8: Private I2C SDR write transfer 0x9: Private I2C SDR read transfer 0xC: Private HDR Double-Data Rate (DDR) write transfer 0xD: Private HDR DDR read transfer 0xE: Servicing IBI transfer 0xF: HALT state In Slave mode of operation: 0x0: IDLE (Controller is in IDLE state) 0x1: Hot-Join transfer state 0x2: IBI transfer state 0x3: Master write transfer ongoing 0x4: Read data prefetch state 0x5: Master read transfer ongoing 0x6: HALT state |
| CM_TFR_ST_STS | Current Master Transfer State Status This field indicates the state of current transfer currently being executed by the I3C. This is valid in Master mode only. 0 (Val_0x0): IDLE (Controller is in IDLE state, waiting for commands) 1 (Val_0x1): START generation state 2 (Val_0x2): RESTART generation state 3 (Val_0x3): STOP generation state 4 (Val_0x4): START hold generation for the slave initiated START state 5 (Val_0x5): Broadcast write address header generation state 6 (Val_0x6): Broadcast read address header generation state 7 (Val_0x7): Dynamic address assignment state 8 (Val_0x8): Slave address generation state 11 (Val_0xB): CCC byte generation state 12 (Val_0xC): HDR command generation state 13 (Val_0xD): Write data transfer state 14 (Val_0xE): Read data transfer state 15 (Val_0xF): IBI (SIR) read data state 16 (Val_0x10): IBI auto disable state 17 (Val_0x11): HDR-DDR CRC data generation/receive state 18 (Val_0x12): Clock extension state 19 (Val_0x13): HALTS state |
| CMD_TID | This field reflects the Transaction-ID of the current executing command. |
| MASTER_IDLE | This bit reflects whether the I3C Master is in IDLE state or not. This bit is set when all the queues (command, response, IBI) and buffers (transmit and receive) are empty along with the Master state machine is in IDLE state. 0 (Val_0x0): I3C Master is not in IDLE State 1 (Val_0x1): I3C Master is in IDLE State |